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? 2016 microchip technology inc. ds20005568a-page 1 MIC24045 features ? 4.5v to 19v input voltage range ? 5a (maximum) output current ?i 2 c programmable output voltage: - 0.64v to 5.25v in 5 mv, 10 mv, 30 mv and 50 mv steps ? high efficiency (>95%) ?i 2 c programmability of: - soft-start: 0.16, 0.38, 0.76 and 1.5v/ms ramp rates - switching frequency: 310 khz, 400 khz, 500 khz, 570 khz, 660 khz, 780 khz, 1 mhz, 1.2 mhz - current limits for 2a, 3a, 4a and 5a loads - output voltage margining: -5%, +5% - start-up delays: 0 ms to 10 ms ? 1% output voltage accuracy over temperature (0.64v to 1.95v) ? supports safe start-up with pre-biased output ? extensive diagnostics through i 2 c interface applications ? servers, data storage, routers and base stations ? fpgas, dsp and low-voltage asic power general description the MIC24045 is an i 2 c-programmable, high-effi- ciency, wide input range, 5a synchronous step-down regulator. the MIC24045 is perfectly suited for multiple voltage rail application environments, typically found in computing and telecommunication systems. in the MIC24045 various parameters can be programmed via i 2 c, such as output voltage, switching frequency, soft-start slope, margining, current limit values and start-up delays. the wide switching frequency adjustment range, valley current-mode control tech- nique, high-performance error amplifier and external compensation allow for the best trade-offs between high efficiency and the smallest possible solution size. the MIC24045 supports extensive diagnostics and status information through i 2 c. the MIC24045 pinout is compatible with the mic24046 pin-strapping programmable regulator pinout, such that i 2 c-based implementations can be easily converted into pin-programmable ones. the MIC24045 is available in a thermally-efficient, space-saving 20-pin 3 mm x 3 mm fqfn package, with an operating junction temperature range from -40c to +125c. typical application lx bst v out 0.64v to 5.25v v dda adr1 a gnd adr0 comp en outsns MIC24045 v in v in 4.5v to 19v p gnd v ddp v inldo v dda address selection v dda v dda enable pg p good scl sda i 2 c i 2 c programmable, 4. 5v-19v input, 5a step-down converter
MIC24045 ds20005568a-page 2 ? 2016 microchip technology inc. package types functional block diagram outsns 2 p gnd p gnd v in comp a gnd lx p gnd bst pg adr0 sda v inldo v ddp v dda en v in 20 1 19 18 17 3 4 14 13 12 11 6789 5 10 15 16 lx adr1 scl MIC24045 3x3fqfn* (top view) 21 v in_ ep 23 lx_ep 22 p gnd_ ep * includes exposed thermal pad (ep); see table 3-1 . control logic/ valley current mode modulator reference and dac uvlo gate drive low-side isense low-side current limit current limit lx gm error amplifier en p gnd i 2 c interface and registers pg sda linear regulator a gnd outsns comp scl adr0 adr1 oscillator and slope compensation v dda v in thermal shutdown and warning v ddp bst i sense high-side current limit hs ls power-good comparator enable comparator v inldo r2 r1 ref dac 2 a uvlo v dda por uvlo clk slope v in outsns soft- start 10o ref dac dly 1.21v v out range ss<1:0> freq<2:0> ilim<1:0> v out <7:0> thsd, thwrn v in _ep lx_ep p gnd _ep
? 2016 microchip technology inc. ds20005568a-page 3 MIC24045 1.0 electrical characteristics absolute maximum ratings ? v in , v inldo, v lx to a gnd ........................................................................................................................... -0. 3v to +20v v ddp , v dda to a gnd ............................................................................................................................... ...... -0.3v to +6v v inldo to v dda ............................................................................................................................... ........... -0.3v to +20v v ddp to v dda ............................................................................................................................... ............. -0.3v to +0.3v v adrx , v sda, v scl to a gnd ......................................................................................................................... -0.3v to +6v v bst to v lx ............................................................................................................................... ................... -0.3v to +6v v bst to a gnd ............................................................................................................................... .............. -0.3v to +26v v en to a gnd .............................................................................................................................. -0.3v to v dda +0.3v,+6v v pg to a gnd ............................................................................................................................... .................. -0.3v to +6v v comp, v outsns to a gnd ......................................................................................................... -0.3v to v dda +0.3v,+6v a gnd to p gnd ............................................................................................................................... ............ -0.3v to +0.3v junction temperature ........................................................................................................... ............................... +150c storage temperature (t s ) ...................................................................................................................... -65c t o +150c lead temperature (soldering, 10s) .............................................................................................. .......................... 260c esd rating ( 1 ) hbm ............................................................................................................................ ........................................... 2000v cdm ............................................................................................................................ ........................................... 2000v note 1: devices are esd sensitive. handling precautions recommended. human body model, 1.5 k ? in series with 100 pf. operating ratings ( 1 ) supply voltage (v in, v inldo ) ......................................................................................................................... 4.5v to 19v externally applied analog and drivers supply voltage (v inldo =v dda =v ddp ) ........................................ 4.5v to 5.5v enable voltage (v en ) .............................................................................................................................. ....... 0v to v dda power-good (pg) pull-up voltage (v pu_pg )................................................................................................... 0v to 5.5v output current ................................................................................................................. ............................................ 5a junction temperature (t j ) ..................................................................................................................... -40c to +125c note 1: the device is not ensured to function outside the operating range. ? notice: stresses above those listed under ?maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational sections of this specification is not intended. exposure to maximum rating conditions for extended periods may affect device reliability.
MIC24045 ds20005568a-page 4 ? 2016 microchip technology inc. electrical characteristics ( note 1 ) electrical specifications: unless otherwise specified, v in =v inldo = 12v; c vdda =2.2f, c vddp =2.2f, t a =+25c. boldface values indicate -40c ? t j ? +125c. parameter symbol min. typ. max. units test conditions v in supply input range v in 4.5 ? 19 v disable current i vinq ?0.2 2 a en = 0v disable current i vinldoq ?0.6 1 ma en = 0v operating current i vinop ? 0.3 0.5 ma en > 1.28v, ilim<1:0> = 00, outsns = 1.15 x v out(nom) , no switching, t a =t j =+25c operating current i vinldoop ?4.5 7 ma en > 1.28v, outsns = 1.15 x v out(nom) , no switching, t a =t j =+25c v dda 5v supply operating voltage v dda 4.8 5.1 5.4 vi vdda = 0 ma to 10 ma dropout operation 3.6 4.2 ? v v inldo = 4.5v, i vdda =10ma v dda undervoltage lockout v dda uvlo rising uvlo_r 3.1 3.5 3.9 vv dda rising, en > 1.28v v dda uvlo falling uvlo_f 2.87 3.2 3.45 vv dda falling, en > 1.28v v dda uvlo hysteresis uvlo_h ? 300 ? mv en control en rising threshold en_r 1.14 1.21 1.28 v initiates power-stage operation en falling threshold en_f ? 1.07 ? v stops power-stage operation en hysteresis en_h ? 135 ? mv en pull-down current en_i 1 2 3 a t a =t j = +25c switching frequency programmable frequency 0 f s0 270 310 350 khz programmable frequency 1 f s1 350 400 450 khz programmable frequency 2 f s2 450 500 550 khz programmable frequency 3 f s3 510 570 630 khz programmable frequency 4 f s4 590 660 740 khz programmable frequency 5 f s5 680 780 880 khz programmable frequency 6 f s6 850 970 1100 khz programmable frequency 7 f s7 1050 1200 1350 khz overcurrent protection hs current limit 0 i lim_hs0 4.0 4.7 6.5 a hs current limit 1 i lim_hs1 5.4 6.2 7.6 a hs current limit 2 i lim_hs2 7.6 8.6 10.6 a hs current limit 3 i lim_hs3 8.2 9.4 12.0 a high side fet current-limit leading edge-blanking time leb ? 108 ? ns ls current limit 0 i lim_ls0 2.0 3.25 5.0 a ls current limit 1 i lim_ls1 3.0 4.3 6.0 a ls current limit 2 i lim_ls2 4.0 5.6 7.5 a note 1: specification for packaged product only.
? 2016 microchip technology inc. ds20005568a-page 5 MIC24045 ls current limit 3 i lim_ls3 5.0 6.2 8.5 a oc events count for hiccup in hicc_de ?15?clock cycles number of subsequent cycles in current limit before entering hiccup overload protection. hiccup wait time t hicc_wait ?13.5v/ ss_srx ? ms duration of the high-z state on lx before new soft-start. ss_srx = ss_sr0, ss_sr1, ss_sr2, ss_sr3 power switches low side fet on resistance r ls ?1621m ? v in =v inldo =v ddp =v dda =5v, v bst -v lx =5v, t a =t j =+25c high side fet on resistance r hs ?3850m ? v in =v inldo =v ddp =v dda =5v, v bst -v lx =5v, t a =t j =+25c pulse-width modulation (pwm) minimum lx on time t on(min) ?26?nst a =t j =+25c minimum lx off time t off(min) 90 145 190 ns v in =v inldo =v dda =5v, v outsns = 3v, 400 khz setting, v out =3.3v, t a =t j =+25c minimum duty cycle d min ?0?%v outsns >1.1xv out(nom) gm error amplifier error-amplifier transconductance gm ea ?1.4? ms error-amplifier dc gain a ea ? 50000 ? v/v error-amplifier source current i sr ? 400 ? a error-amplifier sink current i snk ? 400 ? a comp output swing high comp_h ? 2.5 ? v comp output swing low comp_l ? 0.8 ? v comp-to-inductor current transconductance gm ps ?12.5?a/vv out =1.2v, i out =4a output voltage dc accuracy minimum programmable out- put voltage minout ? 0.64 ? v maximum programmable out- put voltage maxout ? 5.25 ? v lsb for range 0.640v to 1.280v lsb1 ? 5 ? mv lsb for range 1.290v to 1.950v lsb2 ? 10 ? mv lsb for range 1.980v to 3.42v lsb3 ? 30 ? mv lsb for range 4.75v to 5.25v lsb4 ? 50 ? mv output voltage accuracy for ranges 1 and 2 outerr12 -1 ? 1 % 4.75v ? v in ? 19v, v out = 0.64v to 1.95v t a =t j = -40c to +125c, i out =0a electrical characteristics ( note 1 ) electrical specifications: unless otherwise specified, v in =v inldo = 12v; c vdda =2.2f, c vddp = 2.2 f, t a =+25c. boldface values indicate -40c ? t j ? +125c. parameter symbol min. typ. max. units test conditions note 1: specification for packaged product only.
MIC24045 ds20005568a-page 6 ? 2016 microchip technology inc. output voltage accuracy for range 3 and 4 outerr34 -1.5 ? 1.5 % 4.75v ? v in ? 19v for v out = 1.98v to 3.42v, 6v ? v in ? 19v for v out = 4.75v to 5.25v, t a =t j = -40c to +125c, i out =0a load regulation loadreg ? 0.2 ? % i out = 0a to 5a, v out =3.3v line regulation linereg ? 0.1 ? % 6v < v in <19v, i out = 2a internal soft-start reference soft-start slew rate 0 ss_sr0 ? 0.16 ? v/ms v out = 0.64 to 1.28v reference soft-start slew rate 1 ss_sr1 ? 0.38 v/ms v out = 0.64 to 1.28v reference soft-start slew rate 2 ss_sr2 ? 0.76 v/ms v out = 0.64 to 1.28v reference soft-start slew rate 3 ss_sr3 ? 1.5 v/ms v out = 0.64 to 1.28v power good (pg) pg low voltage pg_v ol ?0.18 0.4 vi (pg) =4ma pg leakage current pg_i leak -1 0.02 1 a v pg =5v pg rise threshold pg_r 90 92.5 95 %v out rising pg fall threshold pg_f 87.5 90 92.5 %v out falling pg rise delay pg_r_dly ? 0.45 ? ms v out rising pg fall delay pg_f_dly ? 80 ? s v out falling thermal shutdown thermal shutdown t shdn ? 160 ? c thermal-shutdown hysteresis t shdn_hyst ?25?c thermal warning threshold t thwrn ? 120 ? c efficiency efficiency ?82.3?%v in = 12v, v out =0.9v, i out =2a, f s = 400 khz, l = 1.2 h, t a =+25c i 2 c interface sda, scl v ih v ih 2??vv dda = 5v (levels are 3.3v compatible) sda, scl v il v il ?? 1vv dda = 5v (levels are 3.3v compatible) sda, scl input high/low current i ih , i il -1 ? 1 a sda output low voltage v ol ??0.4vi sda =3ma electrical characteristics ( note 1 ) electrical specifications: unless otherwise specified, v in =v inldo = 12v; c vdda =2.2f, c vddp =2.2f, t a =+25c. boldface values indicate -40c ? t j ? +125c. parameter symbol min. typ. max. units test conditions note 1: specification for packaged product only.
? 2016 microchip technology inc. ds20005568a-page 7 MIC24045 temperature specifications electrical specifications: unless otherwise specified, v in =v inldo = 12v; c vdda = 2.2 f, c vddp = 2.2 f, t a =+25c. boldface values indicate -40c ? t j ? +125c. parameters sym. min. typ. max. units conditions temperature ranges junction temperature t j -40 ? +125 c storage temperature range t a -65 ? +150 c package thermal resistances thermal resistance, 20ld 3x3 fqfn ? ja ?29 ?c/w
MIC24045 ds20005568a-page 8 ? 2016 microchip technology inc. 2.0 typical characteristic curves note: unless otherwise indicated, v in =12v, f s = 660 khz, i lim =i lim_ls3 , l = 2.2 h, t a =+25c. figure 2-1: operating supply current vs. input voltage, switching. figure 2-2: v dda vs. input voltage. figure 2-3: low-side current limits vs. input voltage. figure 2-4: enable thresholds vs. input voltage. figure 2-5: operating supply current vs. temperature, switching. figure 2-6: outsns voltage vs. temperature. note: the graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. the performance characteristics listed herein are not tested or guaranteed. in some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. 0 10 20 30 491419 operating supply current (ma) input voltage (v) v out = 1.0v i out = 0 ma f s = 310 khz f s = 660 khz f s = 1.2 mhz 3.5 4 4.5 5 5.5 491419 v dda voltage (v) input voltage (v) i vdda = 0 ma i vdda = 10 ma 0 2 4 6 8 491419 low-side current limits (a) input voltage (v) i lim_ls3 i lim_ls1 f s = 660 khz v out = 1.0v i lim_ls0 i lim_ls2 1 1.1 1.2 1.3 4 9 14 19 enable thresholds (v) input voltage (v) turn-on turn-off 0 10 20 30 -40 -25 -10 5 20 35 50 65 80 95 110 125 operating supply current (ma) temperature (c) v out = 1.0v i out = 0 ma f s = 1.2 mhz f s = 660 khz f s = 310 khz 0.994 0.995 0.996 0.997 0.998 -40-25-10 5 203550658095110125 outsns voltage (v) temperature (c) v out = 1.0v i out = 0 ma f s = 660 khz
? 2016 microchip technology inc. ds20005568a-page 9 MIC24045 note: unless otherwise indicated, v in =12v, f s = 660 khz, i lim =i lim_ls3 , l = 2.2 h, t a =+25c. figure 2-7: outsns voltage vs. temperature. figure 2-8: outsns voltage vs.temperature. figure 2-9: outsns voltage vs.temperature. figure 2-10: r ds(on) vs. temperature. figure 2-11: error amplifier transconductance vs. temperature. figure 2-12: error amplifier output current vs. temperature. 1.796 1.797 1.798 1.799 1.8 1.801 1.802 -40 -25 -10 5 20 35 50 65 80 95 110 125 outsns voltage (v) temperature (c) v out = 1.8v i out = 0 ma f s = 660 khz 3.297 3.298 3.299 3.3 3.301 3.302 3.303 3.304 3.305 -40 -25 -10 5 20 35 50 65 80 95 110 125 outsns voltage (v) temperature (c) v out = 3.3v i out = 0 ma f s = 660 khz 5.001 5.002 5.003 5.004 5.005 5.006 5.007 5.008 5.009 5.01 5.011 5.012 5.013 5.014 -40 -25 -10 5 20 35 50 65 80 95 110 125 outsns voltage (v) temperature (c) v out = 5.0v i out = 0 ma f s = 660 khz 10 20 30 40 50 60 -40 -25 -10 5 20 35 50 65 80 95 110 125 switch r dson (m ) temperature (c) low side high side 1 1.1 1.2 1.3 1.4 1.5 -40 -25 -10 5 20 35 50 65 80 95 110 125 err. amp. transconductance (ms) temperature (c) -600 -400 -200 0 200 400 600 -40-25-10 5 203550658095110125 error amp. output current ( a) temperature (c) sourcing sinking
MIC24045 ds20005568a-page 10 ? 2016 microchip technology inc. note: unless otherwise indicated, v in =12v, f s = 660 khz, i lim =i lim_ls3 , l = 2.2 h, t a =+25c. figure 2-13: efficiency vs. load current. figure 2-14: efficiency vs. load current. figure 2-15: efficiency vs. load current. figure 2-16: efficiency vs. load current. figure 2-17: efficiency vs. load current. figure 2-18: efficiency vs. load current. 50 55 60 65 70 75 80 85 90 95 100 012345 efficiency (%) i out (a) vout=0.8v vout=1.0v vout=1.2v vout=1.5v vout=1.8v vout=3.3v v out = 0.8v v out = 1.0v v out = 1.2v v out = 1.5v v out = 1.8v v out = 3.3v v in = 5v f s = 310 khz 50 55 60 65 70 75 80 85 90 95 100 012345 efficiency (%) i out (a) vout=0.8v vout=1.0v vout=1.2v vout=1.5v vout=1.8v vout=3.3v vout=5v v out = 0.8v v out = 1.0v v out = 1.2v v out = 1.5v v out = 1.8v v out = 5.0v v in = 12v f s = 310 khz v out = 3.3v 50 55 60 65 70 75 80 85 90 95 100 012345 efficiency (%) i out (a) vout=0.8v vout=1.0v vout=1.2v vout=1.5v vout=1.8v vout=3.3v v out = 0.8v v out = 1.0v v out = 1.2v v out = 1.5v v out = 1.8v v out = 3.3v v in = 5v f s = 660 khz 40 50 60 70 80 90 100 012345 efficiency (%) i out (a) vout=0.8v vout=1.0v vout=1.2v vout=1.5v vout=1.8v vout=3.3v vout=5v v in = 12v f s = 660 khz v out = 0.8v v out = 1.0v v out = 1.2v v out = 1.5v v out = 1.8v v out = 5.0v v out = 3.3v 50 55 60 65 70 75 80 85 90 95 100 012345 efficiency (%) i out (a) series1 series2 series3 series4 series5 series6 v out = 1.2v v out = 0.8v v out = 1.0v v out = 1.5v v out = 1.8v v out = 3.3v v in = 5v f s = 1.2 mhz 40 50 60 70 80 90 100 012345 efficiency (%) i out (a) vout=0.8v vout=1.0v vout=1.2v vout=1.5v vout=1.8v vout=3.3v vout=5v v out = 0.8v v out = 1.0v v out = 1.2v v out = 1.5v v out = 1.8v v out = 5.0v v in = 12v f s = 1.2 mhz v out = 3.3v
? 2016 microchip technology inc. ds20005568a-page 11 MIC24045 note: unless otherwise indicated, v in =12v, f s = 660 khz, i lim =i lim_ls3 , l = 2.2 h, t a =+25c. figure 2-19: load regulation: outsns voltage vs. i out . figure 2-20: load regulation: outsns voltage vs. i out . figure 2-21: load regulation: outsns voltage vs. i out . figure 2-22: load regulation: outsns voltage vs. i out . 0.993 0.994 0.995 0.996 0.997 0.998 0.999 012345 outsns voltage (v) i out (a) v out = 1.0v f s = 660 khz 1.798 1.799 1.8 1.801 1.802 012345 outsns voltage (v) i out (a) v out = 1.8v f s = 660 khz 3.302 3.303 3.304 3.305 3.306 3.307 012345 outsns voltage (v) i out (a) v out = 3.3v f s = 660 khz 5.01 5.011 5.012 5.013 5.014 5.015 5.016 5.017 5.018 5.019 5.02 012345 outsns voltage (v) i out (a) v out = 5v f s = 660 khz
MIC24045 ds20005568a-page 12 ? 2016 microchip technology inc. note: unless otherwise indicated, v in =12v, f s = 660 khz, i lim =i lim_ls3 , l = 2.2 h, t a =+25c. figure 2-23: v in turn-on (en = v dda , no i 2 c programming, registers default values for 2z version), r load =0.3 ? . figure 2-24: v in turn-off (en = v dda ), r load =0.3 ? . figure 2-25: en turn-on, r load =0.3 ? . figure 2-26: en turn-off, r load =0.3 ? . figure 2-27: en turn-on into pre-biased output (v pre-bias =0.5v). figure 2-28: en turn-on into pre-biased output (v pre-bias =0.8v). v in 5v/div v out 500 mv/div pg 5v/div 4ms/div il 2a/div v in 5v/div v out 500 mv/div pg 5v/div il 2a/div 4ms/div en 2v/div v out 500 mv/div pg 5v/div il 2a/div 2ms/div en 2v/div v out 500 mv/div pg 5v/div il 2a/div 80 s/div en 2v/div v out 500 mv/div pg 5v/div il 2a/div 2ms/div en 2v/div v out 500 mv/div pg 5v/div il 2a/div 2ms/div
? 2016 microchip technology inc. ds20005568a-page 13 MIC24045 note: unless otherwise indicated, v in =12v, f s = 660 khz, i lim =i lim_ls3 , l = 2.2 h, t a =+25c. figure 2-29: power-up into short circuit, (en = v dda , no i 2 c programming, registers default values for 2z version). figure 2-30: enable into short circuit. figure 2-31: output current limit threshold. figure 2-32: hiccup mode short circuit current limit response. figure 2-33: thermal shutdown response. figure 2-34: recovery from thermal shutdown. v in 5v/div v out 500 mv/div pg 5v/div il 2a/div 10 ms/div en 2v/div v out 500 mv/div pg 5v/div il 2a/div 4ms/div v out 1v/div il 5a/div ac coupled i out 5a/div pg 5v/div 1ms/div v out 1v/div il 5a/div ac coupled i out 5a/div pg 5v/div 20 ms/div v out 1v/div sw 10v/div i out 500 ma/div pg 5v/div 100 ms/div v out 1v/div sw 10v/div i out 500 ma/div pg 5v/div 10 ms/div
MIC24045 ds20005568a-page 14 ? 2016 microchip technology inc. note: unless otherwise indicated, v in =12v, f s = 660 khz, i lim =i lim_ls3 , l = 2.2 h, t a =+25c. figure 2-35: switching waveforms - f s = 660 khz, i out =0a. figure 2-36: switching waveforms - f s = 660 khz, i out =5a. figure 2-37: load transient response with i lim =i lim_ls0 . figure 2-38: load transient response with i lim =i lim_ls3 . figure 2-39: line transient response. v out 2mv/div ac coupled il 1a/div v in 5v/div sw 5v/div 1s/div v out 2mv/div ac coupled il 2a/div v in 5v/div sw 5v/div 1s/div v out 50 mv/div ac coupled il 2a/div i out 2a/div pg 5v/div 80 s/div step from 0.2a to 2a v out 100 mv/div ac coupled il 5a/div i out 5a/div pg 5v/div 80 s/div step from 0.5a to 5a v out 5mv/div ac coupled v in 2v/div pg 5v/div 1ms/div step from 11.8v to 13.2v
? 2016 microchip technology inc. ds20005568a-page 15 MIC24045 note: unless otherwise indicated, v in =12v, f s = 660 khz, i lim =i lim_ls3 , l = 2.2 h, t a =+25c. figure 2-40: voltage loop gain bode plot, v out = 1.8v, f s = 570 khz, l = 1.2 h, c out =266f, r c1 = 2.55k ? , c c1 = 10nf, c c2 = 47pf (see section 7.7, compensation design ).
MIC24045 ds20005568a-page 16 ? 2016 microchip technology inc. 3.0 pin description the descriptions of the pins are listed in tab l e 3 - 1 . 3.1 input voltage pin (v in ) input voltage pin for the buck converter power stage. these pins are the drain terminal of the internal high-side n-channel mosfet. a 10 f minimum ceramic capacitor should be connected from v in to the p gnd pins as close as possible to the device. a combi- nation of multiple ceramic capacitors of different sizes is recommended. 3.2 power ground pin (p gnd ) low-side mosfet source terminal and low-side driver return. connect the ceramic input capacitors to p gnd as close as possible to the device. 3.3 switch node pin (lx) drain (low-side mosfet) and source (high-side mosfet) connection of the internal power n-channel fets. the external inductor (switched side) and bootstrap capacitor (bottom terminal) must be connected to these pins. 3.4 bootstrap capacitor pin (bst) supply voltage for the driver of the high-side n-channel power mosfet. connect the bootstrap capacitor (top terminal) to this pin. 3.5 power good output pin (pg) when the output voltage is within 92.5% of the nominal set point, this pin will go from logic low to logic high through an external pull-up resistor. this pin is the drain connection of an internal n-channel fet. 3.6 i 2 c address programming pin 0 (adr0) three-state pin (low, high and high-z) for i 2 c address programming. together with adr1, adr0 defines nine logic values corresponding to nine i 2 c addresses. 3.7 i 2 c address programming pin 1 (adr1) three-state pin (low, high and high-z) for i 2 c address programming. together with adr0, adr1 defines nine logic values corresponding to nine i 2 c addresses. table 3-1: pin function table MIC24045 symbol pin function 1, 2 v in input voltage pin 3, 4, 13 p gnd power ground pin 5, 6 lx switch node pin 7 bst bootstrap capacitor pin. a bootstrap capacitor is connected between the bst and lx pins. 8 pg power good open-drain output pin 9 adr0 i 2 c address programming pin 0 10 adr1 i 2 c address programming pin 1 11 scl i 2 c clock input pin 12 sda i 2 c data input/output pin 14 a gnd analog ground pin 15 comp transconductance error amplifier output pin. connect the com- pensation network from comp to a gnd . 16 outsns output sensing pin 17 en precision enable input pin 18 v dda internal regulator output pin 19 v ddp mosfet drivers internal supply pin 20 v inldo internal regulator input pin 21 v in_ ep v in exposed pad. electrically connected to v in. 22 p gnd_ ep p gnd exposed pad. electrically connected to p gnd . 23 lx_ep lx exposed pad. electrically connected to lx.
? 2016 microchip technology inc. ds20005568a-page 17 MIC24045 3.8 i 2 c clock input pin (scl) the scl pin is the serial interfaces serial clock pin.this pin is connected to the host controllers scl pin. the MIC24045 is a slave device, so its scl pin accepts only external clock signals. 3.9 i 2 c data input/output pin (sda) the sda pin is the serial interface serial data pin. this pin is connected to the host controllers sda pin. the sda pin has an open-drain n-channel driver. 3.10 analog ground pin (a gnd ) this pin is a quiet ground for the analog circuitry of the internal regulator and a return terminal for the external compensation network. 3.11 transconductance error amplifier output pin (comp) connect a compensation network from this pin to a gnd . 3.12 output sensing pin (outsns) connect this pin directly to the buck converter output voltage. this pin is the top side terminal of the internal feedback divider. 3.13 precision enable input pin (en) the en pin is compared to a 1.21v typical threshold to determine the turn-on of the device. after reaching the turn-on threshold, the i 2 c-programmable turn-on delay counter starts. a 2 a (typical) current source pulls down the en pin to prevent unwanted power delivery in case of a floating en input. a 135 mv typical hysteresis prevents chattering when power delivery is started. 3.14 internal regulator output pin (v dda ) output of the internal linear regulator and internal sup- ply for analog control. a 1 f minimum ceramic capac- itor should be connected from this pin to a gnd ; a 2.2 f typical value is recommended. 3.15 mosfet drivers internal supply pin (v ddp ) internal supply rail for the mosfet drivers, fed by the v dda pin. an internal resistor (10 ? ) between the v ddp and v dda pins is provided in the regulator in order to implement an rc filter for switching noise suppression. a 1 f minimum ceramic capacitor should be connected from this pin to p gnd ; a 2.2 f typical value is recommended. 3.16 internal regulator input pin (v inldo ) this pin is typically connected to the input voltage of the buck converter stage (v in ). if v inldo and v in are connected to different voltage rails, individually bypass v inldo to ground with a 100 nf ceramic capacitor. 3.17 p gnd exposed pad (p gnd_ep ) electrically connected to p gnd pins. connect with thermal vias to the ground plane to ensure adequate heat-sinking. see section 9.0 ?packaging information? . 3.18 v in exposed pad (v in_ex ) electrically connected to v in pins. if an input power dis- tribution plane is available, connect with thermal vias to that plane to improve heat-sinking. see section 9.0 ?packaging information? . 3.19 lx exposed pad (lx_ep) electrically connected to lx pins. see section 9.0 ?packaging information? .
MIC24045 ds20005568a-page 18 ? 2016 microchip technology inc. 4.0 functional description the MIC24045 is a digitally programmable, 5a valley current-mode controlled regulator featuring an input voltage range from 4.5v to 19v. programmability is achieved by means of an i 2 c-compatible serial digital interface, which can support serial clock (scl) rates up to 400 khz (fast mode). the MIC24045 requires a minimal amount of external components. only the inductor, supply decoupling capacitors and compensation network are external. the flexibility in the external compensation design allows the user to optimize their design across the entire range of operating parameters such as input voltage, output voltage, switching frequency and load current. 4.1 theory of operation valley current-mode control is a fixed-frequency, leading-edge-modulated pwm current-mode control. differing from peak current mode, in valley current-mode the clock marks the turn-off of the high-side switch. upon this instant, the MIC24045 low-side switch current level is compared against the reference current signal from the error amplifier. when the falling low-side switch current signal drops below the current reference signal, the high-side switch is turned on. as a result, the inductor valley current is regulated to a level dictated by the output of the error amplifier. as shown in section 7.7 ?compensation design? , the feedback loop includes an internal programmable reference (ref dac ) and an output voltage sensing attenuator (r2/r1), which removes the need for exter- nal feedback components and improves regulation accuracy. output voltage feedback is achieved by con- necting outsns directly to the output. the high-per- formance transconductance error amplifier drives an external compensation network at the comp pin. the comp pin voltage represents the reference current signal. the comp pin voltage is fed to the valley cur- rent-mode modulator, which also adds slope compen- sation to ensure current-loop stability. valley current-mode control requires slope compensation at duty cycles less than 50% for current-loop stability. the slope compensation circuit is internal and it is automat- ically adapted in amplitude depending upon the fre- quency, output voltage range and voltage differential (v in - v outsns ). the internal low-r ds(on) power mosfets, the associated adaptive gate driver and the internal bootstrap diode complete the power train. overcurrent protection and thermal shutdown protect the MIC24045 from faults or abnormal operating conditions. 4.2 internal ldo, supply rails (v in , v inldo , v dda , v ddp ) v in pins represent the power train input. these pins are the drain connection of the internal high-side mosfet and should be bypassed to p gnd with a x5r or x7r 10 f (minimum) ceramic capacitor, placed as close as possible to the device. a combination of ceramic capacitors of different sizes is recommended. an internal ldo (biased through v inldo pin) provides a clean supply (5.1v typical) for the analog circuits and the i 2 c interface at pin v dda . the internal ldo is typi- cally powered from the same power rail feed at v in ; however, v inldo can also be higher or lower than v in and can be connected to any other voltage within its recommended limits. v inldo and v dda should be locally bypassed (see section 3.0 ?pin description? ). a small series resistor (typically 2 ? -10 ? ) can be used in combination with the v inldo bypass capacitor to implement a rc filter for suppression of large high-fre- quency switching noise. the internal ldo is always enabled and regulation takes place as soon as enough voltage has established between the v inldo and v dda pins. if an external 5v10% is available, it is possible to bypass the inter- nal ldo by connecting v inldo , v dda and v ddp together at the external 5v rail, thus improving overall efficiency. the MIC24045 does not require a separate supply for the i 2 c interface and for the internal logic registers, which are all powered from the v dda rail. an internal undervoltage lock-out circuit (uvlo) monitors the level of v dda and resets the interface and the internal registers if the v dda voltage is below the uvlo threshold. v ddp is the power supply rail for the gate drivers and bootstrap circuit. this pin is subject to high-current spike with high-frequency content. to prevent these from pol- luting the analog v dda supply, a separate capacitor is needed for v ddp pin bypassing. an internal 10 ? resistor is provided between pins v dda and v ddp, allowing a switching noise attenuation rc filter with the minimum amount of external components to be implemented. it is possible, although typically not necessary, to lower the rc time constant by connecting an external resistor between pins v dda and v ddp .
? 2016 microchip technology inc. ds20005568a-page 19 MIC24045 4.3 enable (en) the en pin starts/stops the power delivery to the out- put. it does not turn off the internal ldo. the en pin does not act as a reset signal for the i 2 c registers, only the v dda uvlo circuit does. rising threshold is a precise 1.21v70 mv. a 135 mv typical hysteresis prevents chattering due to switching noise and/or slow edges. a 2 a typical pull-down cur- rent with 1 a accuracy prevents unwanted start-ups if the en pin is momentarily floating. to achieve auto- matic turn-on as soon as enough voltage is present, connect en to v dda . 4.4 power good (pg) pg is an open-drain output. for asserting a logic high level, pg requires an external resistor connected to a pull-up voltage (v pu_pg ), which should not exceed 5.5v. pg is asserted with a typical delay of 0.45 ms when the output voltage (outsns) reaches 92.5% of its target regulation voltage. pg is de-asserted with a typical delay of 80 s when the output voltage falls below 90% of its target regulation voltage. the pg falling delay acts as a de-glitch timer against very short spikes. the pg output is always immediately de-asserted when the en pin is below the power delivery enable threshold (en_r/en_f). the pull-up resistor should be large enough to limit the pg pin current to below 2 ma. the pg is in a defined state once the v dda voltage is greater than about 1v, but with reduced current sinking capability. the pg is also immediately de-asserted (with no delay) whenever an undervoltage condition on v dda is detected, or in thermal shutdown. 4.5 inductor (lx) and bootstrap (bst) the external inductor is connected to lx. the high-side mosfet driver circuit is powered between bst and lx by means of an external capacitor (typically 100 nf) that is replenished from rail v ddp during the low-side mosfet on-time. the bootstrap diode is internal. 4.6 output sensing (outsns) and compensation (comp) outsns should be connected exactly to the desired point-of-load regulation, avoiding parasitic resistive drops. the impedance seen into outsns is high (tens of k ? or more, depending on the selected output volt- age value), therefore its loading effect is typically neg- ligible. outsns is also used by the slope compensation generator. comp is the connection for the external compensation network. comp is driven by the output of the transcon- ductance error amplifier. care must be taken to return the compensation network ground directly to a gnd . 4.7 soft-start the MIC24045 features four different i 2 c-selectable soft-start slew-rate values (0.16v/ms, 0.38v/ms, 0.76v/ms and 1.5v/ms). see the section section 5.0 ?registers maps and i2c programmability? for the value vs. code mapping. the internal reference is ramped up at the selected rate. note that this is the internal reference soft-start slew rate and that the actual slew rate seen at the output should take into account the internal divider attenuation, as detailed in the section 7.0 ?application information? . 4.8 start-up delay the MIC24045 features eight different i 2 c-selectable start-up delays (from 0 ms to 10 ms). these represent the added delays from the en rising edge to the begin- ning of the power delivery (soft-start). see the section section 5.0, registers maps and i2c programma- bility for the value vs. code mapping. 4.9 switching frequency the MIC24045 features eight different i 2 c-selectable switching frequencies from 310 khz to 1200 khz. see section 5.0 ?registers maps and i2c programma- bility? for the value vs. code mapping. also pay atten- tion to voltage conversion ratio limitations due to minimum t on and t off , as stated in section 7.0 ?application information? . 4.10 pre-biased output start-up the MIC24045 is designed to achieve safe start-up into a pre-biased output without discharging the output capacitors. 4.11 thermal warning and thermal shutdown the MIC24045 has a thermal shutdown protection that prevents operation at excessive temperature. the ther- mal shutdown threshold is typically set at +160c with a hysteresis of +25c. the MIC24045 features a thermal warning flag that is readable through the i 2 c interface (register polling is needed). the thermal warning flag signals the approaching of thermal shutdown, so that appropriate system-level countermeasures can be undertaken. note that a thermal shutdown event will not disable the internal v dda linear regulator, but only the power stage. in this way, the i 2 c interface remains powered and can still be read throughout the duration of the thermal shut- down.
MIC24045 ds20005568a-page 20 ? 2016 microchip technology inc. 4.12 overcurrent protection the MIC24045 features instantaneous cycle-by-cycle current limit with current sensing both on the low-side and high-side switches. it also offers a hiccup mode for prolonged overloads or short-circuit conditions. low-side cycle-by-cycle protection detects the current level of the inductor current during the low-side mos- fet on time. the high-side mosfet turn-on is inhib- ited as long as the low-side mosfet current limit is above the low-side current-limit threshold level. the inductor current will continue decaying until the current falls below the threshold, then the high-side mosfet will be enabled again according to the duty cycle requirement from the pwm modulator. the mechanism is illustrated in figure 4-1 . figure 4-1: low-side cycle-by-cycle current-limit action. the low-side current limit is programmable at four different levels (for 2a, 3a, 4a and 5a loads) in order to optimize inductor size for different application requirements. these levels are listed in section 5.0 ?registers maps and i2c programmability? . since the low-side current limit acts on the valley cur- rent, the dc output current level (i out ), where the low-side cycle-by-cycle current limit is engaged, will be higher than the current limit value by an amount equal to ? il pp /2, where ? il pp is the peak-to-peak inductor ripple current. the high-side current limit is approximately 1.4 ? 1.5 times greater than the low-side current limit (typical val- ues). the high-side cycle-by-cycle current limit immedi- ately truncates the high-side on time without waiting for the off clocking event. a leading edge blanking (leb) timer (108 ns, typical) is provided on the high-side cycle-by-cycle current limit to mask the switching noise and to prevent falsely trigger- ing the protection. high-side cycle-by-cycle current limit action cannot take place before the leb timer expires. hiccup mode protection reduces power dissipation in permanent short-circuit conditions. on each clock cycle, where a low-side cycle-by-cycle current-limit event is detected, a 4-bit up/down counter is incre- mented. on each clock cycle, without a concurrent low-side current limit event, the counter is decremented or left at zero. the counter cannot wrap-around below 0000 and above 1111 . high-side current limit events do not increment the counter. only detections from low-side current limit events trigger the counter. if the counter reaches 1111 (or 15 events), the high and low-side mosfets become tri-stated and power delivery to the output is inhibited for a duration which is dependent on the soft-start rate and can be calculated with the following equation: equation 4-1: this digital integration mechanism provides immunity to the momentary overloading of the output. after the wait time, the MIC24045 retries entering operation and initiates a new soft-start sequence. note that hiccup mode short-circuit protection is active at all times, including the soft-start ramp. in case of very large output capacitors, consider slowing down the soft-start slew rate to prevent start-up problems, espe- cially if the load is completely discharging the output capacitor during the hiccup wait time. time i l valley cm clock (hs off, ls on) low-side current-limit threshold ls current ok hs turn-on is enabled ls oc detected hs turn-on inhibited required duty cycle resulting duty cycle ls oc detected hs turn-on inhibited i lpp i out inhibited time 13.5v ss_srx ----------------- - = where ss_srx = selected soft-start rate (ss_srx = ss_sr0, ss_sr1, ss_sr2 or ss_sr3). see electrical characteristics table.
? 2016 microchip technology inc. ds20005568a-page 21 MIC24045 figure 4-2: hiccup short-circuit protection flowchart. start clear ls oc events counter clock pulse (marking hs turn-off, ls turn-on) idle loop in normal operation ls oc event detected? event counter = 0 decrement event counter event counter full? increment event counter initiate hiccup sequence stop switching hs and ls wait inhibited time clear ls oc events counter initiate soft-start enable switching yes yes yes no no no
MIC24045 ds20005568a-page 22 ? 2016 microchip technology inc. 5.0 registers maps and i 2 c programmability the MIC24045 internal registers are summarized in table 5-1 , below. table 5-1: MIC24045 register map register address register name type b7 b6 b5 b4 b3 b2 b1 b0 0h status ro ocf thsdf thwrnf reserved ens reserved reserved pgs 1h setting 1 rw ilim1 ilim0 freq2 freq1 freq0 reserved reserved reserved 2h setting 2 rw reserved sudly2 sudly1 sudly0 mrg1 mrg0 ss1 ss0 3h vout rw vout7 vout6 vout5 vout4 vout3 vout2 vout1 vout0 4h command rw reserved reserved reserved reserved reserved reserved reserved clff
? 2016 microchip technology inc. ds20005568a-page 23 MIC24045 5.1 status register in the read-only status registers, diagnostic informa- tion is provided. bits can be f = latched (flag) or s = non-latched (status). flag bits are set when the corresponding fault condi- tion has occurred and do not return-to-zero once the fault condition has ceased. flags can only be cleared by writing ? 1 ? in bit 0 of the command register 4h, or by power cycling. status bits are set when the corre- sponding fault condition has occurred and return to zero automatically once the fault condition has ceased. default bits value at power-up is zero, except for bit 2 (which will always be read as ? 1 ?) and bit 1, which is ? 1 ? if no fault conditions are detected. register 5-1: status ? status register (address 0h) r-0 r-0 r-0 r?0? r-0 r?1? r-1 r-0 ocf thsdf thwrnf reserved ens reserved reserved pgs bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown rc = read-then-clear bit bit 7 ocf: over-current flag bit. ocf is set high whenever an over-current event occurs. latched. bit 6 thsdf: thermal shut-down flag bit. thsdf is set high whenever a thermal shutdown occurs. latched. bit 5 thwrnf: thermal warning flag bit. thwrnf is set high whenever a thermal warning occurs. latched. bit 4 reserved: flag bit. always read as zero. bit 3 ens: enable pin status bit. ens reflects the logic value present on pin en. non-latched. bit 2 reserved: status bit. always read as ? 1 ?. bit 1 reserved: default status at por is ? 1 ? (no faults detected). bit 0 pgs: power-good status bit. pgs reflects the logic value present on pin pg. non-latched. register 5-2: setting 1 ? setting 1 register (address 1h) rw-v rw-v rw-v rw-v rw-v u-0 u-0 u-0 ilim1 ilim0 freq2 freq1 freq0 reserved reserved reserved bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown rc = read-then-clear bit v = factory-programmed por value ( 1 ) note 1: default status settings at power-up can be changed at the factory. standard selections are described in section 6.0 ?MIC24045 default settings values at power-up? . overwriting default settings by i 2 c has no permanent effect and values will return to factory default values upon power cycling. 2: changing setting 1 register values while power delivery is enabled is not recommended. to change set- tings by i 2 c, set en pin low first, then write the new configuration, and finally, set en pin high again to resume power delivery.
MIC24045 ds20005568a-page 24 ? 2016 microchip technology inc. bit 7-6 ilim<1:0>: mosfet current limit bit. see the current limit selection in table below : bit 5-3 freq0 (switching frequency): see the switching frequency selection in table below: bit 2-0 reserved: unimplemented bit. read as ? 0 ?. register 5-2: setting 1 ? setting 1 re gister (address 1h) (continued) note 1: default status settings at power-up can be changed at the factory. standard selections are described in section 6.0 ?MIC24045 default settings values at power-up? . overwriting default settings by i 2 c has no permanent effect and values will return to factory default values upon power cycling. 2: changing setting 1 register values while power delivery is enabled is not recommended. to change set- tings by i 2 c, set en pin low first, then write the new configuration, and finally, set en pin high again to resume power delivery. ilim1 ilim0 typ low-side current limit (a) typ high-side current limit (a) nominal load current (a) 00 3.25 4.7 2 01 4.3 6.2 3 10 5.6 8.6 4 11 6.2 9.4 5 freq2 freq1 freq0 frequency (khz) 000 310 001 400 010 500 011 570 100 660 101 780 110 970 111 1200
? 2016 microchip technology inc. ds20005568a-page 25 MIC24045 register 5-3: setting 2 ? setting 2 register (address 2h) u-0 rw-v rw-v rw-v rw-0 rw-0 rw-v rw-v reserved sudly2 sudly1 sudly0 mrg1 mrg0 ss1 ss0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown rc = read-then-clear bit v = factory-programmed por value ( 1 ) bit 7 reserved: unimplemented bit. read as ? 0 ?. writing to this bit has no effect. bit 6-4 sudly<2:0>: start-up delay bit. delay to start power delivery from the rising edge of the en signal. see the start-up delay selection in table below: bit 3-2 mrg<1:0>: voltage margins bit. these bits can be changed at any time during power delivery. see the voltage margining selection in table below: bit 1-0 ss1<1:0>: soft-start ramp rate bit. see the soft-start tamp rates selection in table below: note 1: for all bits (except margining bits mrg<1:0>) the default status at power-up can be changed at the factory. standard selections are described in section 6.0 ?MIC24045 default settings values at power-up? . overwriting default settings by i 2 c has no permanent effect and values will return to factory default set- tings upon power cycling. default power-up status for mrg<1:0> is <0:0>. 2: with the exception of margining bits mrg<1:0>, changing setting 2 register values while power delivery is enabled is not recommended. to change settings by i 2 c, set en pin low first, then write the new configuration, and finally, set en pin high again to resume power delivery. sudly2 sudly1 sudly0 start-up delay (ms) 000 0 001 0.5 010 1 011 2 100 4 101 6 110 8 111 10 mrg1 mrg0 change to nominal v out setting (%) 00 0% 01 -5% 10 +5% 11 +5% default at power-up is <0:0> ss1 ss0 soft-start slope (v/ms) 00 0.16 01 0.38 10 0.76 11 1.5
MIC24045 ds20005568a-page 26 ? 2016 microchip technology inc. register 5-4: vout ? vout register (address 3h) rw-v rw-v rw-v rw-v rw-v rw-v rw-v rw-v vout7 vout6 vout5 vout4 vout3 vout2 vout1 vout0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown rc = read-then-clear bit v = factory-programmed por value ( 1 ) bit 7-0 vout<7:0>: vout register bits can be changed at any time during power delivery, provided that tran- sitions from one code to another: ? are done step-by-step, by small vout increments. the speed of the transition is left to the user and limited by the i 2 c writing interface speed. ? code transition shall take place only within the same vout range. crossing boundaries of resolution ranges may cause vout glitches and it is not recommended. see vout selection in table below: note 1: default status settings at power-up can be changed at the factory. standard selections are described in section 6.0 ?MIC24045 default settings values at power-up? . overwriting default settings by i 2 c has no permanent effect and values will return to factory default values upon power cycling. 2: the functionality of the MIC24045 at any output voltage selection is subject to limitations described in section 7.0 ?application information? . register 5-5: command ? command register (address 4h) rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 reserved reserved reserved reserved reserved reserved reserved clff bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown rc = read-then-clear bit bit 7-1 reserved<7:1>: writing to these bits has no effect to the device operation. bit 0 clff: clear fault flags bit. writing ? 1 ? to bit 0 will clear all fault flags. the clff bit is self-clearing and it returns to ? 0 ? as soon as the fault flags have been cleared. vout range step size codes-decimal (hex) 0.640v to 1.280v 5 mv 0 (00h) to 128 (80h) 1.290v to 1.950v 10 mv 129 (81h) to 195 (c3h) 1.980v to 3.420v 30 mv 196 (c4h) to 244 (f4h) 4.750v to 5.250v 50 mv 245 (f5h) to 255 (ffh)
? 2016 microchip technology inc. ds20005568a-page 27 MIC24045 6.0 MIC24045 default settings values at power-up part number MIC24045-xxyfl also designates different default settings values at power-up, before any i 2 c writing operation takes place. these values are programmed at factory. different default settings are obtained by burning an otp memory (fuses). the xx code corresponds to a certain combination of output voltage, switching frequency, nominal load current and soft-start ramp rate. start-up delay and voltage margining always default to 0 ms and 0%. the blank (all zeros) otp memory option has a special code ( 2z ). the standard default settings are as shown in table 6-1 . for availability of other default settings, contact the nearest microchip sales office. when power is cycled, the MIC24045 user-programmable registers return to the factory-programmed default settings values, regardless of any prior settings through i 2 c bus. note that the en pin does not act as a reset signal for the user-programmable registers, only the internal por (power-on reset) based on the v dda voltage uvlo does (see functional block diagram ). table 6-1: standard default settings full part number code v out (v) frequency load current reference soft-start rate MIC24045-2zyfl 2z 0.64 310 khz 2a 0.16v/ms MIC24045-diyfl di 1.0 780 khz 5a 0.38v/ms MIC24045-eiyfl ei 1.2 780 khz 5a 0.38v/ms MIC24045-jfyfl jf 3.3 570 khz 5a 0.38v/ms MIC24045-kdyfl kd 5.0 570 khz 3a 0.38v/ms
MIC24045 ds20005568a-page 28 ? 2016 microchip technology inc. 7.0 application information 7.1 programming external uvlo the en pin can be used to program an automatic turn-on of the MIC24045 when the v in (or v inldo ) power rails have exceeded a desired threshold. this programmable uvlo function is achieved as described in figure 7-1 . figure 7-1: programmable external uvlo function. the programmed v in uvlo threshold v in_rise is given by: equation 7-1: to desensitize the v in uvlo threshold against varia- tions of the pull-up current en_i, it is recommended to run the r1-r2 voltage divider at a significantly higher current level than the en_i current. the corresponding v in uvlo hysteresis, v in_hys, is calculated as follows: equation 7-2: 7.2 output voltage sensing to achieve accurate output voltage regulation, the outsns pin (internal feedback divider top terminal) should be kelvin-connected as close as possible to the point-of-regulation top terminal. since both the internal reference and the internal feedback divider?s bottom terminal refer to a gnd , it is important to minimize voltage drops between the a gnd and the point-of-regulation return terminal. 7.3 v out on-the-fly changes it is possible to change the output voltage on-the-fly during power delivery by writing a different value to register 5-4 (address 3h). note that v out changes are possible only within each v out range, as specified in the vout selection table in register 5-4 . the transition from one particular v out value to another is under control of the i 2 c interface. the num- ber of steps from one code to another and the speed of the transition are left to the end user. single write instructions separated by a repeated start (sr) can be used to update register 5-4 multi- ple subsequent times, without releasing the i 2 c bus. please refer to section section 8.5.2 ?single write with repeated start (sr)? for more details. the minimum t su_sta specification (set-up time for a repeated start condition), the scl frequency and the length of the single write message (3 bytes) dictate a limitation on the maximum update rate of the vout code at register 5-4 . ramping down the output voltage at no or light load implies inductor current reversal (i.e., the MIC24045 will be sinking current from the output capacitor). the larger the output capacitor value, the larger the reverse inductor current will be for a given negative v out vari- ation.the voltage steps and the ramping step rate should be small enough to maintain a safe level of reverse current magnitude. this is especially important when using large output capacitors. 7.4 inductor selection and slope compensation when selecting an inductor, it is important to consider the following factors: ? inductance ? rated current value ? size requirements ? dc resistance (dcr) ? core losses en enable comparator r2 r1 en_i 2 a a gnd en_r 1.21v v inldo enable power delivery 135 mv v in v in_rise en_r 1 r2 r1 ------ - + ?? ?? en_i r2 ? + ? = where: en_r = 1.21v en_i = 2 a ri, r2 = external resistors v in_hys 135 mv 1 r2 r1 ------ - + ?? ?? ? =
? 2016 microchip technology inc. ds20005568a-page 29 MIC24045 the inductance value is critical to the operation of MIC24045. since the MIC24045 is a valley current-mode regulator, it needs a slope compensation for the stable current loop operation where duty cycles are below 50%. slope compensation is internally programmed according to the frequency, output voltage and nominal load current selection, assuming there is a minimum inductance value for the given operating condition. table 7-1 lists the assumed minimum inductor values recommended for stable current-loop operation. note that the minimum suggested inductance values should be met when taking into account the inductor tolerance and its change with current level. the slope compensation is also internally adapted to the input-output voltage differential. in practical implementations of valley current-mode control, slope compensation is also added to any duty cycle larger than 50% as part of improving current loop stability and noise immunity for all input and output volt- age ranges. consequently, the MIC24045 adds internal slope compensation signal up to 80% duty cycle. above this, no slope compensation is added. for this reason, the pwm modulator gain exhibits an abrupt change when the duty cycle exceeds 80%, possibly leading to some increase in jitter and noise susceptibil- ity. if operation around and above 80% duty cycle is considered, a more conservative design of the com- pensation loop might help in reducing jitter and noise sensitivity. inductor current ratings are generally stated as permissible dc current and saturation current. permissible dc current can be rated for a +20c to +40c temperature rise. saturation current can be rated for a 10% to 30% loss in inductance. ensure that the nominal current of the application is well within the permissible dc current ratings of the inductor, depending on the allowed temperature rise. note that the inductor permissible dc current rating typically does not include inductor core losses. these are very important contributors of total inductor core loss and temperature increase in high-frequency dc/dc converters because core losses increase rapidly with the excitation frequency. when saturation current is specified, make sure that there are enough design margins so the peak current does not cause the inductor to enter deep saturation. pay attention to the inductor saturation characteristic in current limit. the inductor should not heavily saturate, even in current limit operation. if there is heavy satura- tion, the current may instantaneously run away and reach potentially destructive levels. typically, ferrite-core inductors exhibit an abrupt saturation char- acteristic, while powdered-iron or composite inductors have a soft-saturation characteristic. peak current can be calculated with equation 7-3 . equation 7-3: as shown in equation 7-3 , the peak inductor current decreases with the switching frequency and the inductance. at a given i out load current, the lower the switching frequency or inductance, the higher the peak current. as input voltage increases, the peak current also increases. 7.5 output capacitor selection two main requirements determine the size and characteristics of the output capacitor c out : ? steady-state ripple ? maximum voltage deviation during load transient for steady-state ripple calculation, both the esr and the capacitive ripple contribute to the total ripple amplitude. table 7-1: minimum recommended inductance values nominal i out v out minimum inductance l min (h) 3a-4a-5a 0.64v-1.28v 1.27 0.97 0.78 0.68 0.58 0.49 0.39 0.29 3a-4a-5a 1.29v-1.95v 1.96 1.51 1.21 1.06 0.91 0.76 0.61 0.45 3a-4a-5a 1.98v-3.42v 3.14 2.42 1.94 1.70 1.46 1.21 0.97 0.73 3a-4a-5a 4.57v-5.25v 3.69 2.36 2.27 1.99 1.70 1.42 1.14 0.85 2a 0.64v-1.28v 2.52 1.94 1.55 1.36 1.16 0.97 0.78 0.58 2a 1.29v-1.95v 4.07 3.13 2.50 2.18 1.87 1.56 1.25 0.94 2a 1.98v-3.42v 6.53 5.03 4.01 3.52 3.02 2.52 2.01 1.51 2a 4.57v-5.25v 9.14 6.99 5.60 4.91 4.18 3.49 2.80 2.10 310 400 500 570 660 780 970 1200 i l,peak i out v out 1v out v in ? ? 2f s ? l ? ----------------------------------- ?? ?? + =
MIC24045 ds20005568a-page 30 ? 2016 microchip technology inc. from the switching frequency, input voltage, output voltage setting, and load current, the peak-to-peak inductor current ripple and the peak inductor current can be calculated as: equation 7-4: equation 7-5: the capacitive ripple ? v r,c and the esr ripple ? v r,esr are given by: equation 7-6: equation 7-7: the total peak-to-peak output ripple is then conservatively estimated as: equation 7-8: the output capacitor value and the esr should be chosen so that ? v r is within specifications. capacitor tolerance should be considered for worst-case calcula- tions. in the case of ceramic output capacitors, factor into account the decrease of effective capacitance versus applied dc bias. the worst-case load transient for output capacitor cal- culation is an instantaneous 100% to 0% load release when the inductor current is at its peak value. in this case, all the energy stored in the inductor is absorbed by the output capacitor while the converter stops switching and keeps the low-side fet on. the peak output voltage overshoot ( ? v out ) happens when the inductor current has decayed to zero. this can be calculated with equation 7-9 : equation 7-9: equation 7-10 calculates the minimum output capacitance value (c out(min) ) needed to limit the output overshoot below ? v out . equation 7-10: the result from the minimum output capacitance value for load transient is the most stringent requirement found for capacitor value in most applications. low equivalent series resistance (esr) ceramic output capacitors, with x5r or x7r temperature characteris- tics, are recommended. for low-output voltage applications with demanding load transient requirements, using a combination of polarized and ceramic output capacitors may be most convenient for smallest solution size. 7.6 input capacitor selection two main requirements determine the size and charac- teristics of the input capacitor: ? steady-state ripple ? rms current the buck converter input current is a pulse train with very fast rising and falling times so low-esr ceramic capacitors are recommended for input filtering, because of their good high-frequency characteristics. for ideal input filtering (assuming a dc input current feeding the filtered buck power stage) and by neglect- ing the capacitor esr contribution to the input ripple (typically possible for ceramic input capacitors), the minimum capacitance value c in(min) needed for a given input peak-to-peak ripple voltage ? v r,in can be estimated as shown in equation 7-11 : equation 7-11: ? i l_pp v out 1v out v in ? ? f s l ? ----------------------------------- ?? ?? = i l,peak i out ? i l_pp 2 ---------------- + = ? v r,c ? i l_pp 8f s ? c out ? --------------------------------- - = ? v r,esr esr ? i l_pp ? = ? v r ? v r,c ? v r,esr + ? ? v out v out 2 l c out ------------- -i l,peak 2 +v out ? = c out(min) l i l,peak 2 ? ? v out v out + ?? 2 v 2 out ? ------------------------------------------------------------------- - = c in(min) i out d ? 1d ? ?? ? ? v r,in f s ? ---------------------------------------------- - = where: d = the duty cycle at the given operating point
? 2016 microchip technology inc. ds20005568a-page 31 MIC24045 the rms current i in,rms of the input capacitor is estimated as in equation 7-12 : equation 7-12: note that, for a given output current i out , the worst-case values are obtained at d = 0.5. multiple input capacitors can be used to reduce input ripple amplitude and/or individual capacitor rms current. 7.7 compensation design as a simple first-order approximation, the valley cur- rent-mode controlled buck power stage can be mod- eled as a voltage-controlled current-source feeding the output capacitor and the load. the inductor current state-variable is removed and the power-stage transfer function from comp to the inductor current is modeled as a transconductance (gm ps ). the simplified model of the control loop is shown in figure 7-2 . the power-stage transconductance gm ps shows some dependence on current levels and it is also somewhat affected by process variations, therefore some design margin is recommended against the typical value gm ps = 12.5a/v (see electrical characteristics ). figure 7-2: simplified small-signal model of the voltage regulation loop. this simplified approach disregards all issues related to the inner current loop, like its stability and bandwidth. this approximation is good enough for most operating scenarios, where the voltage-loop bandwidth is not pushed to aggressively high frequencies. based on the model shown in figure 7-2 , the control-to-output transfer function is: equation 7-13: the MIC24045 uses a transconductance (gm ea = 1.4 ma/v) error amplifier. frequency compensation is implemented with a type-ii network (r c1 , c c1 and c c2 ) connected from comp to a gnd . the compensator transfer function consists of an integrator for zero dc voltage regulation error, a zero to boost the phase margin of the overall loop gain around the crossover frequency and an additional pole that can be used to cancel the output capacitor esr zero, or to further attenuate switching frequency ripple. in both cases, the additional pole makes the regulation loop less susceptible to switching frequency noise. the additional pole is created by capacitor c c2 . equation 7-14 details the compensator transfer function h c(s) (from outsns to comp). equation 7-14: i in, rms i out d1d ? ?? ? ? = r1 v out range r2 ref dac r c1 c c1 c c2 gm ps v in i l v out r l c out gm ea gm error amplifier esr v c comp g co s ?? v out s ?? v cs ?? ------------------- -gm ps r l ? 1 s 2 ? f z ? ---------------- + ?? ?? 1 s 2 ? f p ? ---------------- - + ?? ?? -------------------------------- ? == where: f z , f p = the frequencies associated with the output capacitor esr zero and with the load pole, respectively: f z 1 2 ? c out esr ? ? -------------------------------------------- = f p 1 2 ? c out ? esr r l + ?? ? ------------------------------------------------------------- - = h cs ?? r1 r1 r2 + -------------------- -gm ea 1 sc c1 c c2 + ?? ? ---------------------------------------- - ? ? ? = x 1sr c1 ? c c1 ? + 1sr c1 c c1 c c2 ? c c1 c c2 + -------------------------- - ? ? + ?? ?? ------------------------------------------------------------------- -
MIC24045 ds20005568a-page 32 ? 2016 microchip technology inc. the overall voltage loop gain t v(s) is the product of the control-to-output and the compensator transfer functions: equation 7-15: the value of the attenuation ratio r1/(r1 + r2) depends on the output voltage selection and can be retrieved as illustrated in tab l e 7 - 2 : the compensation design process is as follows: 1. set the t v(s) loop gain crossover frequency f xo in the range f s /20 to f s /10. lower values of f xo allow a more predictable and robust phase mar- gin. higher values of f xo would involve addi- tional considerations about the current loop bandwidth in order to achieve a robust phase margin. taking a more conservative approach is highly recommended. equation 7-16: 2. select r c1 to achieve the target crossover fre- quency f xo of the overall voltage loop. this typ- ically happens where the power stage transfer function g co(s) is rolling off at -20 db/dec. the compensator transfer function h c(s) is in the so-called mid-band gain region where c c1 can be considered a dc-blocking short circuit while c c2 can still be considered as an open circuit, as calculated in equation 7-17 : equation 7-17: 3. select capacitor c c1 to place the compensator zero at the load pole. the load pole moves around with load variations, so, to calculate the load pole, use as a load resistance r l the equiv- alent value that yields the nominal output current i out of the application at the output voltage v out , as shown in: equation 7-18 and equation 7-19 : equation 7-18: equation 7-19: 4. select capacitor c c2 to place the compensator pole at the output capacitor esr zero frequency f z , or at ? 5f xo , whichever is lower. the c c2 is intended for placing the compensator pole at the frequency of the output capacitor esr zero, and/or achieve additional switching ripple/noise attenuation. if the output capacitor is a polarized one, its esr zero will typically occur at low enough frequencies to cause the loop gain to flatten out and not roll-off at a -20 db/decade slope around, or just after the crossover frequency f xo . this causes undesirable scarce compensation design robustness and switching noise susceptibility. the compensator pole is then used to cancel the output capacitor esr zero and achieve a well-behaved roll-off of the loop gain above the crossover frequency. if the output capacitors are only ceramic, then the esr zeroes frequencies could be very high. in many cases, the frequencies could even be above the switching fre- quency itself. loop gain roll-off at -20 db/decade well beyond the crossover frequency is ensured, but even in this case, it is good practice to still make use of the compensator pole to further attenuate switching noise, while conserving phase margin at the crossover fre- quency. for example, setting the compensator pole at 5 f xo , will limit its associated phase loss at the cross- over frequency to about 11. placement at even higher frequencies n f xo (n > 5) will reduce phase loss even further, at the expense of less noise/ripple attenuation at the switching frequency. some attenuation of the switching frequency noise/ripple is achieved as long as nf xo < f s . table 7-2: internal feedback divider attenuation values v out range r1/(r1 + r2) a (a=1+r2/r1) 0.640v ? 1.280v 1 1 1.290v ? 1.950v 0.5 2 1.980v ? 3.420v 0.333 3 4.750v ? 5.250v 0.2 4 t vs ?? g co s ?? h cs ?? ? = f xo f s 20 ----- - ? r c1 r1 r2 + r1 -------------------- - ?? ?? 2 ? c out ? f xo ? gm ea gm ps ? ----------------------------------------- - ? = r l v out i out ------------- = c c1 c out esr r l + ?? ? r c1 ------------------------------------------------- - =
? 2016 microchip technology inc. ds20005568a-page 33 MIC24045 for polarized output capacitor, compensator pole placement at the esr zero frequency is achieved, as shown in equation 7-20 below: equation 7-20: for ceramic output capacitor, compensator pole place- ment at n f xo (n ? 5, n f xo < f s ) is achieved, as detailed in equation 7-21 : equation 7-21: 7.8 output voltage soft-start rate the MIC24045 features internal, i 2 c programmable soft-start, such that the output voltage can be smoothly increased to the target regulation voltage. the soft-start rate given in the electrical characteristics refers to the error amplifier reference, and therefore the effective soft-start rate value seen at the output of the module has to be scaled according to the internal feedback divider attenuation values listed in table 7-2 . to calcu- late the effective output voltage soft-start slew rate ss_sr out , based on the particular output voltage set- ting and the reference soft-start slew rate ss_srx (x = 0, 1, 2, 3 depending on selection), use the follow- ing formula: equation 7-22: 7.9 minimum t on and minimum t off limitations the valley current-mode control method utilized in the MIC24045 allows very small minimum controllable on time (around 26 ns), so that it is possible to convert from 19v down to very low voltages at high frequency. note that the high-side current limit circuit may not be able to detect an overcurrent event if the on time is below the high side switch current limit leading edge blanking time (leb, see electrical characteristics ). conversely, some minimum off time is needed for valley current-mode modulator operation. this t off(min) specification (see electrical characteristics ) may dictate a limit on the maximum attainable output voltage for a given v in voltage. the maximum attainable output voltage (at no load) is calculated as follows: equation 7-23: it is advisable to use a safe headroom margin against the calculated value of v out,max for dc load and good dynamic performance. c c2 1 r c1 c out esr ? ------------------------------- 1 c c1 --------- - ? ----------------------------------------------- - = c c2 1 2 ? r c1 ? n ? f xo 1 c c1 --------- - ? ? --------------------------------------------------------------- - = ss_sr out a ss_srx ? = where: a = amplification (see tab l e 7 - 2 for a values.) v out,max v in 1f s t off(min) ? ? ?? ? =
MIC24045 ds20005568a-page 34 ? 2016 microchip technology inc. 8.0 i 2 c interface description the i 2 c bus is for 2-way, 2-line communication between different ics or modules. the two lines are: a serial data line (sda) and a serial clock line (scl). both lines must be connected to a positive supply via a pull-up resistor. data transfer may be initiated only when the bus is not busy. MIC24045 is a slave-only device (i.e., it cannot generate a scl signal and does not have scl clock stretching capability). every data transfer to and from the MIC24045 must be initiated by a master device which drives the scl line. the MIC24045 is a fast mode device, supporting data transfers at up to 400 kbit/s. the MIC24045 device assumes that the i 2 c logic levels on the bus are generated by a device operating from a nominal supply voltage of 3.3v (with +/-10% tolerance). therefore, v ih and v il are not related to the v dda value of the MIC24045. the sda and scl lines must not be pulled up to the v dda voltage of the MIC24045, but to the i 2 c master interface supply voltage (3.3v nominal). figure 8-1: bit transfer. 8.1 bit transfer one data bit is transferred during each clock pulse. the data on the sda line must remain stable during the high period of the clock pulse as changes in the data line at this time will be interpreted as control signals. 8.2 start and stop conditions both data and clock lines remain high when the bus is not busy. a high-to-low transition of the data line while the clock is high is defined as the start (s) or repeated start (sr) condition. a low-to-high tran- sition of the data line while the clock is high is defined as the stop condition (p). start and stop condi- tions are always generated by the master. the bus is considered to be busy after the start condition. the bus is considered to be free again a certain time after the stop condition. the bus stays busy if a repeated start (sr) is generated instead of a stop condition. figure 8-2: start and stop conditions. sda scl data line stable; data valid change of data allowed sda scl s p sda scl start condition stop condition
? 2016 microchip technology inc. ds20005568a-page 35 MIC24045 8.3 device address the MIC24045 device uses a 7-bit address, which is set in hardware, using three-state pins adr0 and adr1 (high, low, or high-z). these two three-state pins allow for nine different addresses, as described in table 8-1 below. 8.4 acknowledge the number of data bytes transferred between the start and the stop conditions, from transmitter to receiver, is not limited. each byte of eight bits is fol- lowed by one acknowledge bit. the acknowledge bit is a high level put on the bus by the transmitter, whereas the master generates an extra acknowledge-related clock pulse. the device that acknowledges has to pull down the sda line during the acknowledge clock pulse, so that the sda line is stable low during the high period of the acknowledge-related clock pulse; setup and hold times must be taken into account. a slave receiver which is addressed must generate an acknowledge after the reception of each byte. also, a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter, except on the last received byte. a master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave transmitter. in this event, the transmitter must leave the data line high to enable the master to generate a stop condition. 8.5 bus transactions 8.5.1 single write the first seven bits of the first byte make up the slave address. the eighth bit is the lsb (least significant bit). it determines the direction of the message (r/w). a ?zero? in the least significant position of the first byte means that the master will write information to a selected slave. a ? 1 ? in this position means that the master will read information from the slave. when an address is sent, each device in a system compares the first seven bits after the start condition with its address. if they match, the device considers itself addressed by the master as a slave-receiver or slave-transmitter, depending on the r/w bit. command byte is a data byte which selects a register on the device. the least significant six bits of the com- mand byte determine the address of the register that needs to be written. the data to port is the 8-bit data that needs to be written to the selected register. this is followed by the acknowledge from the slave and then the stop condi- tion. the write command is as follows and it is illustrated in the timing diagram below: 1. send start sequence 2. send 7-bit slave address 3. send the r/w bit - 0 to indicate a write operation 4. wait for acknowledge from the slave 5. send the command byte ? address that needs to be written 6. wait for acknowledge from the slave 7. receive the 8-bit data from the master and write it to the slave register indicated in step 5 starting from msb 8. acknowledge from the slave 9. send stop sequence figure 8-3: single write timing diagram. table 8-1: MIC24045 i 2 c address setting adr1 adr0 i 2 c address 0 0 101 0000 0 1 101 0001 1 0 101 0010 1 1 101 0011 0 high-z 101 0100 high-z 0 101 0101 1 high-z 101 0110 high-z 1 101 0111 high-z high-z 101 1000 0 0 sda scl s 0 a a data 1 a 1 2 3 4 5 6 7 8 9 start condition r/w ack from slave slave address command byte ack from slave ack from slave data to port p data out from port data 1 valid
MIC24045 ds20005568a-page 36 ? 2016 microchip technology inc. 8.5.2 single write with repeated start (sr) in multi-master i 2 c systems, this bus transaction is the recommended method to execute v out on-the-fly changes in multiple steps. the sequence is the same as for the previous single write transaction, except that at the end the master issues a repeated start (sr) instead of a stop (p), and another (or more) single write operation takes place until the master releases the bus with a stop. this way the master does not release the bus after the first single write and can accomplish the v out on-the-fly change in multiple steps, without interference from other master devices. the single write with repeated start (sr) command is as follows and it is illustrated in the timing diagram of figure 8-4 below: 1. send start sequence 2. send 7-bit slave address 3. send the r/w bit - 0 to indicate a write operation 4. wait for acknowledge from the slave 5. send the command byte ? address that needs to be written 6. wait for acknowledge from the slave 7. receive the 8-bit data ? data 1 from the master and write it to the slave register indicated in step 5, starting from msb 8. acknowledge from the slave ? the register is updated with data 1 9. send start sequence 10. send 7-bit slave address 11. send the r/w bit - 0 to indicate a write operation 12. wait for acknowledge from the slave 13. send the command byte ? address that needs to be written 14. wait for acknowledge from the slave 15. receive the 8-bit data ? data 2 from the master and write it to the slave register indicated in step 13, starting from msb 16. acknowledge from the slave ? the register is updated with data 2 these steps (steps 9 through 16) can continue as many times as needed to write to the same register (or another valid writable register as indicated in steps 5 and 13) without sending a stop sequence. the master will conclude the data transfer on the last write operation by generating a stop condition. figure 8-4: single write with repeated start timing diagram. note: writing to a non-existing register location will generate a reject action (nack) by the MIC24045 after the command byte. 0 0 sda scl s 0 a a data 1 a 1 2 3 4 5 6 7 8 9 start r/w ack from slave slave address command byte ack from slave ack from slave 0 0 sda scl sr 0 a a data 2 a 1 2 3 4 5 6 7 8 9 repeated start r/w ack from slave slave address command byte ack from slave ack from slave register address register address 0 0 sda scl sr 0 a a data n a 1 2 3 4 5 6 7 8 9 repeated start r/w ack from slave slave address command byte ack from slave ack from slave register address p stop note: writing to a non-existing register location will generate a reject action (nack) by the MIC24045 after the command byte.
? 2016 microchip technology inc. ds20005568a-page 37 MIC24045 8.5.3 single read this reads a single byte from a device, from a desig- nated register. the register is specified through the command byte. the read command is as follows and it is illustrated in the timing diagram of figure 8-5 below. 1. send start sequence 2. send 7-bit slave address 3. send the r/w bit - 0 to indicate a write operation 4. wait for acknowledge from the slave 5. send the register address that needs to be read 6. wait for acknowledge from the slave 7. send start sequence again (repeated start condition) 8. send the 7-bit slave address 9. send r/w bit - 1 to indicate a read operation 10. wait for acknowledge from the slave 11. receive the 8-bit data from the slave starting from msb 12. acknowledge from the master. on the received byte, the master receiver issues a nack in place of ack to signal the end of the data transfer. 13. send stop sequence figure 8-5: single read timing diagram. sda s 0 a a start condition ack from slave slave address command byte ack from slave sr 1 a a (repeated) start condition r/w ack from slave slave address data from register stop condition data (first byte) r/w at this moment master-transmitter becomes master-receiver and slave-receiver becomes slave-transmitter p (cont.) * * * (cont.) * * * note: attempts to read from a non-existing register location will generate a reject action (nack) by the MIC24045 after the command byte.
MIC24045 ds20005568a-page 38 ? 2016 microchip technology inc. 8.5.4 block read (auto increment mode) this command reads a block of bytes, starting from a designated register that is specified through the com- mand byte. bit<6> of the command byte indicates the auto-increment mode. if this bit is set, the address gets incremented by one automatically and the registers are read in order, starting from the address provided by the command byte. the block/auto-increment read command is as follows and it is illustrated in the timing diagram of figure 8-6 . 1. send start sequence 2. send 7-bit slave address 3. send the r/w bit - 0 to indicate a write operation 4. wait for acknowledge from the slave 5. send the command byte ? address that needs to be read with bit<6> set high to indicate the auto-increment read mode. 6. wait for acknowledge from the slave 7. send start sequence again 8. send the 7-bit slave address 9. send r/w bit - 1 to indicate a read operation 10. wait for acknowledge from the slave 11. receive the 8-bit data from the slave register indicated in step 5, starting from msb 12. acknowledge from the master receiver. on the last byte, master receiver issues a nack in place of ack to signal the end of the data transfer. 13. repeat steps 11 and 12 until last byte 14. stop sequence is sent figure 8-6: block read timing diagram. in block read auto-increment mode, the master receiver must signal an end-of-data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this event, the transmitter must leave the data line high to enable the master to generate a stop condition. if the master keeps reading beyond the valid user-accessible register locations, the content of inter- nal test registers will be streamed out until location 15 (fh) is reached. after that, the read operation wraps-around and restarts from register location 0h and so on, until the master stops reading. sda s 0 a a start condition ack from slave slave address command byte ack from slave sr 1 a a (repeated) start condition r/w ack from slave slave address data from register x+n stop condition data (first byte) r/w at this moment master-transmitter becomes master-receiver and slave-receiver becomes slave-transmitter p * * * (cont.) * * * 1 (cont.) * * * a data from register x data (first byte) data from register x+1 data (first byte) a note: if the master is using a non-existing regis- ter location in the command byte, a reject (nack) will be generated by the MIC24045.
? 2016 microchip technology inc. ds20005568a-page 39 MIC24045 8.5.5 block write (auto-increment mode) this command writes data to the designated register and to all the following registers that are specified through the command byte. bit<6> of the command byte indicates the auto-increment mode. if this bit is set, the address gets incremented by one automatically and the registers are written in order, starting from the address provided by the command byte. the block/auto-increment write command is as follows and it is illustrated in the timing diagram of figure 8-7 below. 1. send start sequence 2. send 7-bit slave address 3. send the r/w bit - 0 to indicate a write operation 4. wait for acknowledge from the slave 5. send the command byte ? address that needs to be written with bit<6> set high to indicate the auto-increment write mode. 6. wait for acknowledge from the slave. 7. receive the 8-bit data from the master and write it to the slave register indicated in step 5, starting from msb. 8. acknowledge from the slave 9. repeat steps 7 and 8 until the entire data is sent 10. send stop sequence figure 8-7: block write timing diagram. 1 0 sda scl s 0 a a a 1 2 3 4 5 6 7 8 9 start condition r/w ack from slave slave address command byte ack from slave data to port p data out from port data 1 valid data 1 ack from slave data to port a data 1 data to port a ack from slave ack from slave data 1 stop condition data 2 valid data n valid note: if the master is using a non-existing register location, a reject (nack) will be generated.
MIC24045 ds20005568a-page 40 ? 2016 microchip technology inc. 9.0 packaging information 9.1 package marking information 20-pin fqfn (3 x 3 mm) legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e example 2z 24045 1612 xx 24045 yyww
? 2016 microchip technology inc. ds20005568a-page 41 MIC24045
MIC24045 ds20005568a-page 42 ? 2016 microchip technology inc. notes:
? 2016 microchip technology inc. ds20005568a-page 43 MIC24045 appendix a: revision history revision a (may 2016) ? original release of this document.
ds20005568a-page 44 ? 2016 microchip technology inc. MIC24045 product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . part no. device device: MIC24045: i 2 c-programmable, high-efficiency, wide input range, 5a synchronous step-down regulator xx = device code for default settings (see ta b l e 6 - 1 ) lead finish y = pb-free with industrial temperature grade package fl = flip-chip qfn, 0.85 mm thickness examples: a) MIC24045-2zyfl: 2z default settings option , pb-free, 20-pin 3 x 3 mm fqfn package. x x - x x x lead finish package code default settings
? 2016 microchip technology inc. ds20005568a-page 45 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights unless otherwise stated. trademarks the microchip name and logo, the microchip logo, anyrate, dspic, flashflex, flexpwr, heldo, jukeblox, keeloq, keeloq logo, kleer, lancheck, link md, medialb, most, most logo, mplab, optolyzer, pic, picstart, pic32 logo, righttouch, spynic, sst, sst logo, superflash and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. clockworks, the embedded control solutions company, ethersynch, hyper speed control, hyperlight load, intellimos, mtouch, precision edge, and quiet-wire are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, any capacitor, anyin, anyout, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dynamic average matching, dam, ecan, ethergreen, in-circuit serial programming, icsp, inter-chip connectivity, jitterblocker, kleernet, kleernet logo, miwi, motorbench, mpasm, mpf, mplab certified logo, mplib, mplink, multitrak, netdetach, omniscient code generation, picdem, picdem.net, pickit, pictail, puresilicon, righttouch logo, real ice, ripple blocker, serial quad i/o, sqi, superswitcher, superswitcher ii, total endurance, tsharc, usbcheck, varisense, viewspan, wiperlock, wireless dna, and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. gestic is a registered trademar ks of microchip technology germany ii gmbh & co. kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2016, microchip technology incorporated, printed in the u.s.a., all rights reserved. isbn: 978-1-5224-0587-0 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 ==
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